This invention relates, in general, to semi-conductor processing and more particularly to a novel method of reliably forming self-aligned contact openings, the method having particular utility in the processing of Very Large Scale Integrated Circuit (VLSIC) devices.
One of the major factors affecting the field of high density integrated circuits (IC) has been the accuracy of alignment of the apertures in the various layers of photoresist both with respect to the direct connections to doped semi-conductor regions, as well as level-to-level alignment for interlevel connections. This problem becomes more troublesome as the density of the IC devices, on a given size chip, and the geometries (gate, drain, and source dimensions) of each device becomes smaller.
One approach toward a solution to this problem appears in a recently issued patent to A. G. F. Dingwall, entitled "BURIED CONTACT CONFIGURATION FOR CMOS/SOS INTEGRATED CIRCUITS", U.S. Pat. No. 4,196,443 ('443) which issued on Apr. 1, 1980 and is assigned to the same assignee as the subject application. In this '443 patent there is described various configurations for buried contact openings that have been formed in the insulating layer overlying a layer of semi-conductor material and through which the buried contact is made. The philosophy behind the '443 patent is to form the opening of the buried contact in a manner so as to preclude the complete removal of the epitaxial silicon material in the event of a major misalignment. Thus, the configuration of the described opening is designed to ensure sufficient contact to the desired area and sufficient silicon to surround the contact region to form a useful device. However, it must be recognized that the '443 patent does not eliminate the removal of epitaxial silicon in the event of a misalignment.
To preclude the inadvertent removal of epitaxial silicon one would look to a recent patent which issued in the name of Martin A. Blumenfeld entitled "METHOD OF FABRICATING BURIED CONTACTS", U.S. Pat. No. 4,373,254 ('254) which issued on Feb. 15, 1983 and is assigned to the same assignee as the subject application. The philosophy behind the process of the '254 patent is to precondition an area surrounding the buried contact by doping. Thereafter, the contact opening is made smaller than the preconditioned area and the '254 process does not have to pay the penalty of forming an undesired junction thus rendering the device inoperative. However, while not having to pay certain penalties, the art would not look to either the '254 or the '443 patents for a solution to the misalignment in a VLSI circuit device due to the fact that the designer does not have the luxury of forming excessively broad protective bands, as suggested by the '254 process. Similarly, it would not be feasible to look to the '443 process due to the fact that this process does not address the problem of conservation of "real estate" where chip area is so valuable.